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Welcome to the RISC-V Port Project!

RISC-V is the free and open RISC instruction set architecture developed by the RISC-V Foundation. RISC-V ISA is actually a family of related ISAs of which there are currently four base ISAs [1].

Those base ISAs can be combined with a set of standard extensions. RV64G and RV32G are defined as general-purpose ISAs. RISC-V ISA needs a new OpenJDK port.

We have ported JDK to a new platform: Linux/RISC-V. This port supports the following subsystems:

• The template interpreter
• The C1 (client) JIT compiler
• The C2 (server) JIT compiler
• All current mainline GCs, including Z and Shenandoah

Currently, this port only supports RV64GV, i.e., RV64G ISA plus the "V" standard extension for vector operations. In the future, this port may support other ISA variants like RV32G depending on community interest.

We are building nightlies here [2]. And we've provided build instructions for reference [3].

You can try the RISC-V JDK with QEMU User/System mode or hardwares like HiFive Unleashed/Unmatched board.

[1] https://github.com/riscv/riscv-isa-manual

[2] https://builds.shipilev.net/openjdk-jdk-riscv

[3] http://cr.openjdk.java.net/~fyang/openjdk-riscv-port/BuildRISCVJDK.md

Project structure

• master branch - synced automatically with the master branch of openjdk/jdk
• riscv-port branch - for normal riscv-port project development purpose

Resources

• RISC-V Port Project
• Repository
• Mailing list: riscv-port-dev (archives)